Applicant hereby incorporates by reference Japanese Application No. 2000-382396, filed Dec. 15, 2000, in its entirety.
The present invention relates to a semiconductor devices including a non-volatile memory transistor and method for manufacturing the same.
A transistor having a split-gate structure is known as one of the devices that are applied to an electrically erasable programmable ROM (EEPROM). FIG. 16 schematically shows a cross-sectional view of one example of a conventional semiconductor device including a non-volatile memory transistor.
The semiconductor device includes a non-volatile memory transistor having a split-gate structure (hereafter referred to as a xe2x80x9cmemory transistorxe2x80x9d) 300.
The memory transistor 300 has, in the case of an N-type transistor as an example, a source region 14 and a drain region 16 composed of n+-type impurity diffusion layers formed in the silicon substrate 10 of P-type, and a first dielectric layer 70 as a gate insulation layer formed on a surface of the silicon substrate 10. A floating gate 72, a second dielectric layer 76 and a control gate 78 are successively formed on the first dielectric layer 70.
A third dielectric layer 74 is formed on the floating gate 72. The third dielectric layer 74 is composed of a dielectric layer that is formed by selectively oxidizing a part of a polysilicon layer that becomes the floating gate 72. The third dielectric layer 72 has a structure in which the film thickness thereof becomes thinner from its center toward its end sections, as shown in FIG. 16. As a result, upper edge sections 720 of the floating gate 72 form sharp edges, such that an electric field concentration is apt to occur at the upper edge sections 720.
For the operation of the memory transistor with a split-gate structure 300, a channel current is flown between the source region 14 and the drain region 16 to thereby inject a charge (hot electrons) in the floating gate 72 as indicated by an arrow A10 when data is written. When data is erased, a predetermined high voltage is applied to the control gate 78 to thereby transfer the charge stored in the floating gate 72 through the second dielectric layer 76 to the control gate 78 as indicated by an arrow B10 by Fowler-Nordheim tunneling conduction (FN conduction).
Certain embodiments relate to a semiconductor device having a non-volatile memory transistor. The device includes a semiconductor layer and a floating gate disposed over the semiconductor layer through a first dielectric layer that acts as a gate dielectric layer. The device also includes a second dielectric layer that contacts at least a part of the floating gate and is capable of functioning as a tunneling dielectric layer, and a control gate formed over the second dielectric layer. The device also includes an impurity diffusion layer that forms a source region or a drain region formed in the semiconductor layer. A conduction layer is provided above the floating gate, and the conduction layer entirely overlaps the floating gate.
Embodiments also include a semiconductor having a non-volatile memory transistor device, including a semiconductor layer and a floating gate disposed over the semiconductor layer through a first dielectric layer as a gate dielectric layer. The device also includes a second dielectric layer that contacts at least a part of the floating gate and is capable of functioning as a tunneling dielectric layer, and a control gate formed over the second dielectric layer. The device also includes an impurity diffusion layer that forms a source region or a drain region formed in the semiconductor layer. A plurality of conduction layers are formed at different levels above the floating gate, and the floating gate is entirely overlapped by the plurality of conduction layers as viewed in a plan view.
Embodiments also include to a semiconductor device having a non-volatile memory transistor, including a non-volatile memory transistor including a semiconductor layer, a floating gate disposed above the semiconductor layer, and a control gate formed above the floating gate, wherein a conduction layer is provided vertically above the floating gate at least in a region where the control gate is not disposed vertically above the floating gate.
Embodiments also include to a semiconductor device having a non-volatile memory transistor, comprising a non-volatile memory transistor including a semiconductor layer, a floating gate disposed above the semiconductor layer, and a control gate formed above the floating gate, wherein a conduction layer is provided above the non-volatile memory transistor and a portion of the conduction layer is located vertically above the floating gate. In addition, a width of the conduction layer located vertically above the floating gate is formed to be greater than a width of the floating gate.
Embodiments also include a semiconductor device having a non-volatile memory transistor, including a non-volatile memory transistor including a semiconductor layer, a floating gate disposed above the semiconductor layer, and a control gate disposed above the floating gate, wherein a plurality of conduction layers having a multiple layered structure are provided above the non-volatile memory transistor. In addition, at least one conduction layer among the plurality of conduction layers is provided vertically above the floating gate at least in a region where the control gate is not disposed vertically above the floating gate.
Embodiments also include a semiconductor device having a non-volatile memory transistor, comprising a semiconductor layer and a floating gate disposed over the semiconductor layer through a first dielectric layer that comprises a gate dielectric layer. The device also includes a second dielectric layer that contacts at least a part of the floating gate and comprises a tunneling dielectric layer. In addition, the device includes a control gate formed over the second dielectric layer; and one or more conduction layers formed over the floating gate. The floating gate includes an upper surface, and a line normal to any portion of the upper surface will contact at least one of the one or more conduction layers over the floating gate.
Embodiments also include a method for manufacturing a semiconductor device having a non-volatile memory transistor, including forming a first dielectric layer comprising a gate dielectric layer on a substrate and forming a floating gate over the gate dielectric layer. The method also includes forming a second dielectric layer that contacts at least a part of the floating gate and is capable of functioning as a tunneling dielectric layer. The method also includes forming a control gate over the second dielectric layer and forming an impurity diffusion layer that forms a source region or a drain region in the semiconductor layer. In addition, the method also includes forming a conduction layer above the floating gate so that a portion of the conduction layer is positioned vertically above the floating gate, where the portion of the conduction layer overlaps the entire floating gate.
Embodiments also include a method for manufacturing a semiconductor device having a non-volatile memory transistor, including forming a floating gate above a semiconductor layer, forming a control gate above the floating gate, and forming a conduction layer vertically above the floating gate at least in a region where the control gate is not disposed vertically above the floating gate.
Embodiments also include a method for manufacturing a semiconductor device having a non-volatile memory transistor, including forming a floating gate above a semiconductor layer, forming a control gate above the floating gate, and forming a plurality of conduction layers having a multiple layered structure above the non-volatile memory transistor, wherein at least one of the conduction layers is formed vertically above the floating gate at least in a region where the control gate is not disposed vertically above the floating gate.